1. Field of the Invention
The present invention relates to the method for fabricating a semiconductor device. More particularly, the present invention relates to the method for fabricating a transistor in integrated circuits.
2. Description of the Prior Art
According to conventional knowledge, a transistor of integrated circuits is fabricated by the following method.
Referring to FIG. 1, first, a silicon substrate 11 is provided. Then after a shallow trench isolation (STI) 12 is formed on the substrate 11 by any conventional process, a well (n-type or p-type) 13 is formed on and in the substrate 11 by ion implantation or by any other conventional process. A gate oxide layer 14 is then formed on the substrate by rapid thermal oxidation (RTO) or any other conventional process. Subsequently, a poly-silicon layer 15 is formed on the gate oxide layer 14 by chemical vapor deposition (CVD). After forming a patterned photoresist 16 on the poly-silicon layer 15, an etch process is used to etch the poly-silicon layer 15 and the gate oxide layer 14. Therein the pattern, having the pattern of a gate region, serves as an etching mask to protect the underlying portion of the etched layers. Thereafter, the photoresist 16 is stripped away. The residual poly-silicon layer 15 serves as a gate electrode of a gate in the semiconductor transistor.
Referring to FIG. 2, the poly-silicon layer 15 has a sidewall formed after an etch process. The next step is to introduce ions onto and into the substrate 11 by an ion implantation process to form a lightly doped drain (LDD) region 17.
Referring to FIG. 3, chemical vapor deposition (CVD) or another appropriate process is used to form an oxide liner layer 18 on all surfaces including the top and sidewall of the poly-silicon layer 15, and the top of the substrate 11. Subsequently, a silicon nitride layer 19 is deposited on the oxide liner layer 18 by a chemical vapor deposition (CVD) process and then etched back.
Referring to FIG. 4, the residual silicon nitride layer 19 serves as a spacer against the conductor layer 15 and is about 1000 angstroms thick. Then, ion implantation is used to introduce ions into the lightly doped drain (LDD) region 17 of the substrate 11 to form a source/drain region 20.
Referring to FIG. 5, the exposed silicon surfaces, including the top of the gate electrode 15 and the top of the substrate 11, are treated by a salicidation process. The salicide layer 21 is then completed.
Referring to FIG. 6, the salicide layer 21 is used to reduce the resistance of the silicon surfaces and to facilitate the contact process. In the use of the transistor structure fabricated by this convention method, at least a series resistance appears in the path through which the current is conducted. The series resistance includes a pair of contact resistance R.sub.c, a channel resistance R.sub.ch and a pair of extra resistance R.sub.ext. The contact resistance R.sub.c part, due to nature of salicide, extends from the site at which the node contact is located to the edge of the salicide layer 21 against the nitride spacer 19. The channel resistance R.sub.ch part, existing in the channel region under the gate, extends from edge of the source LDD region to the one of the drain LDD region. And the extra resistance R.sub.ext, existing inside of the LDD region, is located under the nitride spacer (about 1000 angstroms).
According to the trend of reducing the size of integrated circuits, the effects of the series resistance is becoming more and more obvious and can be less and less ignored for the device's driving current. The effects include reducing the running speed of integrated circuits and causing a high temperature during running.
For the foregoing reasons described above, there is a need to develop a method for fabricating a transistor that can reduce the series resistance, particularly the part of the series resistance in the non-salicide region. This improvement would enable the running speed of the integrated circuits to be enhanced, thus the increased temperature during running can be reduced.